How to Simulate Retro CPU Architecture in FPGA Using Verilog: Apple Lisa Recreation Guide

Recreating vintage computer architectures in FPGAs has become increasingly popular among hardware enthusiasts and reverse-engineering hobbyists. The Apple Lisa, one of the earliest graphical user interface computers, represents a fascinating challenge for FPGA developers seeking to understand and preserve computing history. This guide walks you through the essential techniques and tooling required to implement a complete CPU simulation on modern FPGA platforms.

Understanding FPGA Simulation vs. Full Emulation

Before diving into implementation, it's critical to distinguish between running a cycle-accurate simulation and achieving full system functionality. A proper FPGA recreation of the Apple Lisa requires:

• Cycle-accurate CPU behavior: Matching instruction timing of the original Motorola 68000 processor
• Memory mapping: Replicating the original memory layout and addressing schemes
• Peripheral simulation: Implementing graphics controllers, disk controllers, and I/O interfaces
• Clock synchronization: Maintaining proper timing across all subsystems

Many developers underestimate the complexity of peripheral integration, which often requires more effort than the CPU core itself.

Hardware Requirements and Tool Selection

Successfully recreating the Apple Lisa in FPGA demands careful hardware selection. The original Lisa used a Motorola 68000 running at 5 MHz with approximately 1 MB of RAM. Modern FPGA boards offer vastly more resources than necessary, which can be both an advantage and a pitfall.

Recommended FPGA Platforms

| Platform | LUT Count | RAM (Mbits) | Best For | Price Range | |----------|-----------|-------------|----------|-------------| | Lattice iCE40 | 5K-8K | 1-2 | Learning, prototyping | $20-50 | | Xilinx Artix-7 | 54K-950K | 10-46 | Complete system | $50-300 | | Intel Cyclone V | 77K-301K | 12-40 | Production targets | $100-400 | | Gowin GW2A | 20K-21K | 9-18 | Cost-effective full system | $30-80 |

For a complete Apple Lisa simulation, Artix-7 or Cyclone V boards provide sufficient resources without excessive overhead. The original recreation mentioned in recent hardware projects typically uses high-end Xilinx or Intel platforms to handle graphics rendering alongside CPU simulation.

CPU Core Implementation in Verilog

The Motorola 68000 is a 16-bit processor with a 32-bit instruction set—a complexity that makes it more challenging than simpler architectures like the 6502. Here's a minimal instruction decoder structure:

module m68000_core (
  input clk,
  input rst,
  output [23:0] addr_bus,
  inout [15:0] data_bus,
  output [2:0] fc,          // Function code (memory/IO)
  output as_n,              // Address strobe
  output rw                 // Read/Write
);

  reg [31:0] pc;            // Program counter
  reg [31:0] d_reg [0:7];   // Data registers D0-D7
  reg [31:0] a_reg [0:7];   // Address registers A0-A7
  reg [15:0] ir;            // Instruction register
  reg [3:0] cc;             // Condition codes (XNZVC)
  
  // State machine for instruction fetch/execute cycle
  reg [2:0] state;
  localparam FETCH = 3'b000;
  localparam DECODE = 3'b001;
  localparam EXECUTE = 3'b010;
  localparam STORE = 3'b011;
  
  always @(posedge clk) begin
    if (rst) begin
      pc <= 32'h0;
      state <= FETCH;
    end else begin
      case (state)
        FETCH: begin
          // Initiate memory read
          addr_bus <= pc[23:0];
          as_n <= 1'b0;
          fc <= 3'b010;  // Supervisor program space
          state <= DECODE;
        end
        DECODE: begin
          ir <= data_bus;
          state <= EXECUTE;
        end
        EXECUTE: begin
          // Instruction decoding logic
          case (ir[15:12])
            4'b0000: execute_move_sr();
            4'b0001: execute_move_to_ccr();
            // Additional instruction patterns...
          endcase
          state <= FETCH;
          pc <= pc + 2;  // Increment by word
        end
      endcase
    end
  end
  
endmodule

This skeletal structure provides the basic fetch-decode-execute pipeline. Production implementations require full opcode decoding for 1000+ instruction variants supported by the 68000.

Memory Architecture and Mapping

The Apple Lisa's memory map presents specific challenges:

• 0x000000-0x0FFFFF: 1 MB System RAM (later expanded to 2 MB)
• 0x100000-0x1FFFFF: Additional RAM bank
• 0xFEE000-0xFEFFFF: I/O space (graphics, disk, network controllers)
• 0xFF0000-0xFFFFFF: ROM (diagnostic and boot code)

Implementing this in FPGA requires careful block RAM (BRAM) allocation:

module lisa_memory_controller (
  input clk,
  input [23:0] addr,
  inout [15:0] data,
  input rw,
  input as_n,
  output dtack_n
);

  // System RAM using BRAM
  reg [15:0] system_ram [0:524287];  // 1 MB in words
  
  // ROM for diagnostics
  reg [15:0] rom [0:32767];          // 64 KB
  
  // I/O register file
  reg [15:0] io_regs [0:255];
  
  always @(posedge clk) begin
    if (!as_n) begin
      case (addr[23:20])
        4'h0, 4'h1: begin  // RAM space
          if (rw) 
            data <= system_ram[addr[19:1]];
          else
            system_ram[addr[19:1]] <= data;
        end
        4'hF: begin  // ROM space
          data <= rom[addr[15:1]];
        end
        4'hE: begin  // I/O space
          if (rw)
            data <= io_regs[addr[7:1]];
          else
            io_regs[addr[7:1]] <= data;
        end
      endcase
      // Assert data transfer acknowledge
      dtack_n <= 1'b0;
    end
  end
  
endmodule

This memory controller handles bus arbitration and access timing. Real implementations must also account for wait states and DMA operations from graphics and disk subsystems.

Graphics Controller Integration

The Lisa's graphics subsystem represents 40% of the implementation complexity. The system used a 720x360 monochrome display with a dedicated graphics buffer.

Key considerations:

1. Bit-plane rendering: The Lisa stored graphics as packed bits, requiring decompression logic
2. Frame synchronization: Horizontal and vertical blanking intervals must match original timing (60 Hz)
3. Video output: HDMI or VGA conversion requires high-speed pixel clock generation
4. Memory bandwidth: Graphics refresh requires continuous memory access without blocking the CPU

A practical approach uses separate clock domains for CPU (5 MHz) and video (40+ MHz pixel clock), with CDC (Clock Domain Crossing) FIFOs handling data transfer.

Testing and Validation Strategy

Validating your implementation requires three levels of testing:

1. Unit testing: Verify individual instructions against 68000 reference manuals
2. Integration testing: Run diagnostic ROMs from the original Lisa hardware
3. System testing: Execute original Lisa applications like LisaWrite or LisaDraw

Extract diagnostics from original hardware using a bus analyzer or logic analyzer to generate golden reference traces. Compare your simulation outputs cycle-by-cycle against these traces to identify discrepancies.

Common Pitfalls in FPGA Retro Computing

Timing assumptions: The 68000's asynchronous bus protocol includes setup/hold time requirements often overlooked in HDL. Use proper timing constraints in your synthesis tools.

Instruction variants: The 68000 supports addressing modes (postincrement, predecrement, indexed) that multiply instruction count. Incomplete mode support breaks real software.

Peripheral timing: Disk controllers and graphics chips have strict timing requirements. Off-by-one errors in cycle counting cause system hangs that are extremely difficult to debug.

Tools and Development Workflow

For FPGA development targeting retro systems:

• HDL Simulation: ModelSim, Vivado Simulator, or open-source Verilator for pre-synthesis testing
• Synthesis: Vivado (Xilinx), Quartus (Intel), or open-source Yosys
• Version Control: Track your HDL with Git; FPGA projects benefit from detailed commit messages documenting hardware behavior discoveries
• Documentation: Maintain a wiki documenting undocumented hardware behaviors discovered during reverse engineering

Conclusion

Recreating the Apple Lisa in FPGA is an advanced project requiring deep knowledge of 68000 assembly, FPGA architecture, and vintage computer design. Success depends on meticulous attention to timing details, comprehensive testing against original hardware, and patience during the inevitable debugging phases. The intersection of CPU architecture, memory systems, and peripheral integration makes this project ideal for developers ready to move beyond simple projects and understand real hardware design complexity.

Start with a minimal CPU core, gradually add memory and I/O subsystems, and validate each component against original hardware behavior. Modern FPGA tools and open-source reference designs have made such projects far more accessible than a decade ago.